4 ECTS credits
110 h study time

Offer 1 with catalog number 4016977ENR for all students in the 1st semester at a (E) Master - advanced level.

Semester
1st semester
Enrollment based on exam contract
Impossible
Grading method
Grading (scale from 0 to 20)
Can retake in second session
Yes
Taught in
English
Partnership Agreement
Under interuniversity agreement for degree program
Faculty
Faculty of Engineering
Department
Electronics and Informatics
External partners
Université libre de Bruxelles
Educational team
Dragomir Milojevic (course titular)
External teachers
Dragomir Milojevic
Activities and contact hours
12 contact hours Lecture
36 contact hours Seminar, Exercises or Practicals
Course Content

In this course, the students will (1) learn about PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays) digital circuits, (2) gain a global view of what a digital design flow is (for FPGA as well for ASICs), in terms of software tools, vocabulary, key steps and methodology, (3) learn the basics of VHDL hardware design language, (4) practice the full cycle of a FPGA-targeted design (problem analysis, VHDL code design and test, bitstream download onto a commercial FPGA-board).

The valid fiche can be found at the following link:  ELEC - H409
Change the language to English in the dropdown menu on top of the page.


 

Course material
Digital course material (Required) : https://www.biopark.be/programme/cours/2018/ELEC-H409/index.html
Additional info

The valid fiche can be found at the following link:  ELEC - H409
Change the language to English in the dropdown menu on top of the page.

 
Learning Outcomes

Algemene competenties

Understand the main concepts of VHDL language to describe, design and implement a digital system

This course contributes to the following programme outcomes of the Master in Electronics and Information Technology Engineering:

The Master in Engineering Sciences has in-depth knowledge and understanding of
2. integrated structural design methods in the framework of a global design strategy

The Master in Engineering Sciences can
5. conceive, plan and execute a research project, based on an analysis of its objectives, existing knowledge and the relevant literature, with attention to innovation and valorization in industry and society
6. correctly report on research or design results in the form of a technical report or in the form of a scientific paper
7. present and defend results in a scientifically sound way, using contemporary communication tools, for a national as well as for an international professional or lay audience
9. work in an industrial environment with attention to safety, quality assurance, communication and reporting
11. think critically about and evaluate projects, systems and processes, particularly when based on incomplete, contradictory and/or redundant information

The Master in Engineering Sciences has
12. a creative, problem-solving, result-driven and evidence-based attitude, aiming at innovation and applicability in industry and society

The Master in Electronics and Information Technology Engineering:
17. Has an active knowledge of the theory and applications of electronics, information and communication technology, from component up to system level.
18. Has a profound knowledge of either (i) nano- and opto-electronics and embedded systems, (ii) information and communication technology systems or (iii) measuring, modelling and control.
19. Has a broad overview of the role of electronics, informatics and telecommunications in industry, business and society.
21. Is able to model, simulate, measure and control electronic components and physical phenomena.

FPGA/VHDL Design Flow

Understand the main concepts of PLDs and FPGAs circuits, and the associated design flows

VHDL programming

Analyse a problem of information processing in terms of sequential/combinatorial digital systems; create and test a VHDL program to solve it

Grading

The final grade is composed based on the following categories:
Written Exam determines 70% of the final mark.
Practical Exam determines 30% of the final mark.

Within the Written Exam category, the following assignments need to be completed:

  • Written exam with a relative weight of 1 which comprises 70% of the final mark.

    Note: see course website on ULB Moodle for additional details

Within the Practical Exam category, the following assignments need to be completed:

  • Lab presentation with a relative weight of 1 which comprises 30% of the final mark.

    Note: see course website on ULB Moodle for additional details

Additional info regarding evaluation

The valid fiche can be found at the following link:  ELEC - H409
Change the language to English in the dropdown menu on top of the page.

 
Allowed unsatisfactory mark
The supplementary Teaching and Examination Regulations of your faculty stipulate whether an allowed unsatisfactory mark for this programme unit is permitted.

Academic context

This offer is part of the following study plans:
Master of Electrical Engineering: Standaard traject BRUFACE J