5 ECTS credits
130 h study time

Offer 1 with catalog number 4016992ENR for all students in the 2nd semester at a (E) Master - advanced level.

Semester
2nd semester
Enrollment based on exam contract
Impossible
Grading method
Grading (scale from 0 to 20)
Can retake in second session
Yes
Taught in
English
Partnership Agreement
Under interuniversity agreement for degree program
Faculty
Faculty of Engineering
Department
Electronics and Informatics
External partners
Université libre de Bruxelles
Educational team
Dragomir Milojevic (course titular)
External teachers
Dragomir Milojevic
Activities and contact hours
24 contact hours Lecture
36 contact hours Seminar, Exercises or Practicals
Course Content

Analyse basic computer and CPU architecture. Software and hardware views of the execution pipeline. Instruction level parallelism. Understand pipeline hazards and methods to avoid them (forwarding, register renaming, instruction scheduling). Learn about branch handling. Understand the concept of cache memory: basics and cache management. Understand data parallelism: software and hardware views. Study in detail the example of modern CPU micro-architecture (intel). 

The valid fiche can be found at the following link:  ELEC - H473
Change the language to English in the dropdown menu on top of the page.

Course material
Digital course material (Recommended) : http://beams.ulb.ac.be/courses/ma1/microprocessor-architectures
Additional info

Lectures notes availble on :

http://beams.ulb.ac.be/courses/ma1/microprocessor-architectures

Learning Outcomes

General competencies

Master basic and advanced theoretical concepts in the modern CPU micro-architecture

Being able to perform hardware dependent software optimisation

Assembly level programming including SIMD computations

 

This course contributes to the following programme outcomes of the Master in Electronics and Information Technology Engineering:

The Master in Engineering Sciences has in-depth knowledge and understanding of
3. the advanced methods and theories to schematize and model complex problems or processes

The Master in Engineering Sciences can
5. conceive, plan and execute a research project, based on an analysis of its objectives, existing knowledge and the relevant literature, with attention to innovation and valorization in industry and society
6. correctly report on research or design results in the form of a technical report or in the form of a scientific paper
7. present and defend results in a scientifically sound way, using contemporary communication tools, for a national as well as for an international professional or lay audience
8. collaborate in a (multidisciplinary) team
11. think critically about and evaluate projects, systems and processes, particularly when based on incomplete, contradictory and/or redundant information

The Master in Engineering Sciences has
12. a creative, problem-solving, result-driven and evidence-based attitude, aiming at innovation and applicability in industry and society
13. a critical attitude towards one’s own results and those of others

The Master in Electronics and Information Technology Engineering:
17. Has an active knowledge of the theory and applications of electronics, information and communication technology, from component up to system level.
18. Has a profound knowledge of either (i) nano- and opto-electronics and embedded systems, (ii) information and communication technology systems or (iii) measuring, modelling and control.
19. Has a broad overview of the role of electronics, informatics and telecommunications in industry, business and society.
20. Is able to analyze, specify, design, implement, test and evaluate individual electronic devices, components and algorithms, for signal-processing, communication and complex systems.
22. Is aware of and critical about the impact of electronics, information and communication technology on society.

Grading

The final grade is composed based on the following categories:
Other Exam determines 100% of the final mark.

Within the Other Exam category, the following assignments need to be completed:

  • exam with a relative weight of 1 which comprises 100% of the final mark.

Additional info regarding evaluation

 

Practical work accounts for 35% of the final mark.The exam is oral, no handbook allowed, two questions 20min of preparation, 5-10min of presentation and Q&A session.

Allowed unsatisfactory mark
The supplementary Teaching and Examination Regulations of your faculty stipulate whether an allowed unsatisfactory mark for this programme unit is permitted.

Academic context

This offer is part of the following study plans:
Master of Electrical Engineering: Standaard traject BRUFACE J